Profile
Wei Xiangqing
I am a doctoral researcher focusing on hardware–software co-design for deep learning accelerators. My current work builds closed-loop reinforcement-learning-driven scheduling frameworks for NPU and FPGA-based neural network accelerators.
Research Focus
RL-driven Accelerator Scheduling
I study reinforcement-learning-based scheduling methods for neural network accelerators, focusing on tile dispatch, PE allocation, latency reduction, energy efficiency, and utilization improvement.
Tile-level DAG Modeling
I model CNN workloads as tile-level directed acyclic graphs to capture computation dependencies, weight reuse, memory conflicts, and hardware execution constraints.
NPU and FPGA Acceleration
My work involves NVDLA-style and Gemmini-style accelerator modeling, MAC/PE-array analysis, RTL-level instrumentation, and FPGA-based validation.
Memory-aware Optimization
I am interested in RL-driven memory optimization for sparse neural models, including prefetching, bank allocation, data reuse, and irregular memory-access scheduling.
Research Pipeline
Selected Publications
RL-Based Scheduling and Allocation of MAC Units in Multi-Precision Edge CNN Accelerators
Wei Xiangqing, Yun-ju Baek. NOLTA 2025 — International Symposium on Nonlinear Theory and Its Applications, 2025.
Design and Optimization of Integer Divider Based on SRT4
Wei Xiangqing, Qin Shuijie. Microprocessors, Vol. 43, No. 2, pp. 1–5, 2022.
Academic Background
Research Assistant
Chiba University, Japan
Research area: AI accelerators, NPU scheduling, reinforcement learning, FPGA-based accelerator design.
Master’s Degree in Integrated Circuit Engineering
Guizhou University, China
Research area: RISC-V processor design, integer execution units, Booth multiplication,
SRT division, and digital circuit design.
Research Keywords
AI Accelerators NPU FPGA Reinforcement Learning Tile-level Scheduling DAG Modeling Sparse Neural Networks Hardware-Software Co-design Computer Architecture RTL Design